Analog Mixed-Signal Verification: Bridging Digital and Analog Worlds
Analog Mixed-Signal (AMS) verification is the discipline of validating systems that combine analog circuitry (amplifiers, ADCs, DACs, PLLs, regulators) with digital logic (control state machines, calibration engines, register files) on a single chip. Unlike pure digital verification, AMS verification must reconcile two fundamentally different modeling paradigms: continuous-time, continuous-value analog physics and discrete-time, discrete-value digital logic. This guide covers the abstraction levels, modeling languages, co-simulation techniques, and regression strategies that production teams use to sign off mixed-signal SoCs.
Quick Summary
| Core Challenge | Co-simulating continuous analog and discrete digital domains with acceptable speed and accuracy |
| Key Technique | Real Number Modeling (RNM) using wreal / SystemVerilog nettype for event-driven analog behavior |
| Goal | SPICE-level confidence in full-chip context at near-digital simulation speed |
Why AMS Verification Is Hard
Mixed-signal designs break the assumptions that make pure-digital verification tractable. The verification engineer must contend with several intertwined problems:
- Two solvers, one design: Analog blocks are solved by a continuous-time matrix solver (Newton-Raphson on KCL/KVL equations), while digital blocks advance through a discrete event queue. Synchronizing them is the central engineering problem.
- Speed gap: A transistor-level SPICE simulation of a PLL locking can take hours; the digital logic exercising it expects to run millions of cycles in seconds. Naive full-SPICE co-simulation is orders of magnitude too slow for regression.
- Continuous values in a digital flow: Voltages, currents, and gains are real numbers, not
0/1/X/Z. Representing them inside an event-driven simulator requires special net types. - Connectivity correctness: Analog-digital boundary errors (swapped polarity, missing supply, wrong reference) are the single most common silicon respin cause in AMS SoCs and are invisible to digital-only checks.
- Coverage definition: Functional coverage on analog quantities (did we exercise the ADC across its full input range and all gain settings?) has no standard equivalent to digital code coverage.
Abstraction Levels in AMS Verification
The art of AMS verification is choosing the right abstraction for each block so that simulation runs fast enough while preserving the accuracy needed to catch real bugs. The four common levels, from most accurate to most abstract, are:
SPICE / Transistor Level
The analog block is described as a netlist of transistors, resistors, and capacitors solved with a SPICE engine (Spectre, HSPICE, FineSim). This level captures device physics, parasitics, noise, and process corners with the highest fidelity. It is the golden reference but is far too slow for full-chip or long regression runs. Used for characterization and for verifying the analog block in isolation.
Behavioral (Verilog-AMS / VHDL-AMS)
The analog behavior is captured with conservative or signal-flow equations using electrical disciplines and analog branches. This still invokes the analog solver but with far fewer equations than a transistor netlist, giving a meaningful speedup while retaining continuous-time accuracy for quantities like settling and stability.
Real Number Modeling (RNM)
The analog signal is represented as a real-valued voltage (or current) that updates only on events, evaluated entirely inside the digital event-driven kernel with no analog solver invoked. RNM is the workhorse of full-chip AMS regression: it runs at near-digital speed while still modeling realistic analog behavior such as gain, offset, saturation, and quantization.
Behavioral / Functional Digital
At the highest abstraction, the analog block is reduced to an ideal digital function (for example, an ADC modeled as a lookup that converts a real input to a code with no dynamic error). Useful for early architectural validation and for blocks not under test in a given run.
| Abstraction Level | Simulation Engine | Relative Speed | Accuracy | Typical Use |
|---|---|---|---|---|
| SPICE / Transistor | Analog matrix solver | 1x (baseline, slowest) | Highest (device-level) | Block characterization, golden reference |
| Verilog-AMS Behavioral | Analog solver (reduced) | 10x - 100x | High (continuous-time) | Stability, settling, AC behavior |
| Real Number Modeling | Digital event kernel | 1,000x - 10,000x | Medium (event-based real) | Full-chip regression, connectivity |
| Functional Digital | Digital event kernel | 10,000x+ | Low (ideal behavior) | Architecture, early system bring-up |
Real Number Modeling: wreal and nettype
RNM exists because the analog solver is the bottleneck. By representing an analog node as a real value that propagates through the standard digital event queue, the simulator avoids matrix solving entirely. Two generations of constructs are in use:
Verilog-AMS wreal
The original RNM construct is the wreal (wired-real) net. A wreal carries a single real number representing a voltage. Multiple drivers are resolved by a built-in resolution function (the language defines behaviors such as resolveTo`wrealSum or a single-driver assumption). It is simple and widely supported but limited to one scalar quantity per net.
SystemVerilog nettype (User-Defined Nettypes)
IEEE 1800 introduced nettype, a far more powerful mechanism. A user-defined nettype binds a data type (often a struct carrying voltage and current, or impedance) to a user-written resolution function. This enables modeling of bidirectional ports, supply nets with both V and I, and accurate driver contention - things wreal cannot express. Nettypes are the modern recommendation for new RNM models.
RNM Example: wreal and a User-Defined Nettype
// --- Verilog-AMS wreal: simple voltage net ---
module gain_stage(in, out);
input wreal in;
output wreal out;
parameter real gain = 2.0;
assign out = in * gain; // event-driven, no analog solver
endmodule
// --- SystemVerilog nettype: voltage + current ---
typedef struct {
real V; // node voltage
real I; // node current
} elec_t;
// resolution: sum currents, average voltages
function automatic elec_t res_elec(input elec_t drv[]);
res_elec.V = 0.0; res_elec.I = 0.0;
foreach (drv[i]) begin
res_elec.V += drv[i].V;
res_elec.I += drv[i].I;
end
if (drv.size() > 0) res_elec.V = res_elec.V / drv.size();
endfunction
nettype elec_t elec with res_elec; // usable as a real, bidirectional net
Verilog-AMS and VHDL-AMS
Two IEEE-standard hardware description languages support true continuous-time analog modeling alongside digital constructs:
- Verilog-AMS (Accellera / IEEE): Extends Verilog with analog blocks (
analog begin ... end), disciplines (electrical,logic), branch contributions (V(n) <+ ...), and the connect-module infrastructure that links analog and digital domains. Dominant in the Cadence/Synopsys mixed-signal flows. - VHDL-AMS (IEEE 1076.1): Extends VHDL with
quantityandterminalobjects and simultaneous equations (==). Strong typing and conservative-system semantics make it popular in automotive and aerospace modeling.
Both express conservative (Kirchhoff) systems and signal-flow systems. In practice most full-chip flows use a hybrid: Verilog-AMS or VHDL-AMS for the analog islands that still need solver accuracy, RNM for the rest, and SystemVerilog/UVM for the digital testbench.
Analog-Digital Co-Simulation and Connect Modules
When analog and digital nets meet, the simulator must convert between a continuous voltage and a logic value. This boundary is managed by connect modules (also called interface elements, or IEs).
Connect Modules (Connect Rules)
- Electrical-to-Logic (E2L / A2D): Thresholds a real voltage against
VIH/VIL(relative to the supply) to produce a logic0,1, orXin the transition band. - Logic-to-Electrical (L2E / D2A): Drives a real voltage with a defined rise/fall slew and output impedance when the digital side changes state.
- Connect rules map disciplines and direction to the correct connect module automatically, and supply-sensitive variants scale thresholds with the actual rail voltage - critical for power-aware and multi-voltage designs.
Solver Synchronization
The analog and digital kernels exchange state at synchronization points. The analog solver runs to a time point, the digital queue processes events at that time, and the two iterate until convergence before advancing. Poorly placed boundaries (for example, slicing a feedback loop across the A/D interface) cause synchronization thrash that destroys performance - a key reason to push boundaries to natural signal interfaces.
Performance vs Accuracy Trade-offs
There is no single "correct" abstraction - the right choice depends on what each run must prove. A disciplined team maintains multiple views of every analog block (SPICE, AMS behavioral, RNM, functional) and selects per simulation:
- Block sign-off: Transistor-level SPICE for the block under characterization, ideal models for everything else.
- Subsystem verification: AMS behavioral for the block of interest to confirm dynamic behavior, RNM for surrounding blocks.
- Full-chip regression: RNM everywhere for speed, exercising firmware, calibration, and digital control across thousands of vectors.
- Connectivity / LEC: Functional or RNM models, focused on netlist correctness rather than analog precision.
The essential discipline is model equivalence checking: every RNM model must be validated against its SPICE golden reference (DC sweep, transient, corner spot-checks) so that the fast model is trustworthy. An unvalidated RNM model gives fast, confident, wrong answers.
Regression Strategies for AMS
Mixed-signal regression must balance the long runtime of analog-accurate runs against the breadth required for coverage closure:
- Tiered regression: A large fast tier (RNM, every commit) plus a small slow tier (AMS/SPICE, nightly or weekly) on the most sensitive scenarios.
- UVM-driven stimulus: Reuse the digital UVM environment to drive analog blocks through RNM models, randomizing analog parameters (gain, offset, reference voltage) as constrained-random knobs.
- Real-valued functional coverage: Bin continuous quantities (input voltage ranges, gain codes, temperature points) into coverpoints so analog operating space is measurable.
- Corner and Monte Carlo sampling: Run process/voltage/temperature corners and statistical samples on the AMS tier; RNM models parameterized with corner data extend some of this coverage cheaply.
- Self-checking scoreboards: Predict expected analog output (with tolerance bands) and compare automatically, rather than relying on waveform inspection.
Implementation Best Practices
- Validate every RNM model against SPICE: Never trust a fast model that has not been equivalence-checked across DC, transient, and corners. Document the validation as part of sign-off.
- Place A/D boundaries at natural interfaces: Cut at clean signal ports, never inside feedback loops or matched differential pairs, to avoid solver synchronization thrash.
- Prefer SystemVerilog nettype over wreal for new models: Use struct-based nettypes when you need bidirectional ports, current, or accurate driver resolution.
- Make connect rules supply-aware: Scale logic thresholds with the actual rail voltage so multi-voltage and power-gated regions behave correctly.
- Build assertions at the boundary: Add SVA for X-propagation, minimum pulse width, and supply-valid conditions on every analog-digital interface.
- Maintain multiple model views per block: Keep SPICE, AMS behavioral, RNM, and functional views in sync and select per regression tier.
- Define real-valued coverage early: Specify analog coverpoints and tolerance bands in the verification plan, not after first silicon.
Conclusion
AMS verification succeeds when the team treats abstraction as a deliberate, validated engineering choice rather than a default. Real Number Modeling delivers the speed to run firmware and digital control against realistic analog behavior at full-chip scale, while SPICE and Verilog-AMS/VHDL-AMS provide the device-level fidelity needed to characterize and trust those fast models. The connect-module boundary - guarded by supply-aware rules and boundary assertions - is where most silicon-killing bugs are caught.
The recurring lesson is that fast models are only valuable when continuously equivalence-checked against a golden reference; an unvalidated abstraction simply hides the bug. A tiered regression strategy, real-valued coverage, and self-checking scoreboards turn this discipline into measurable, repeatable sign-off confidence.
Vcores offers comprehensive mixed-signal verification services - RNM and nettype model development, Verilog-AMS/VHDL-AMS behavioral modeling, connect-module and co-simulation setup, and full-chip AMS regression - to bring SPICE-level confidence to your mixed-signal SoC at digital simulation speed.
